1. Field of the Invention
The present invention relates to a semiconductor memory device and method of manufacturing the same, and more particularly, to a Static Random Access Memory cell which enhances immunity to soft errors and a manufacturing method thereof.
2. Description of the Related Art
A semiconductor memory device is classified into a Dynamic Random Access Memory (DRAM) and a Static Random Access Memory (SRAM) according to its method of storing data. The SRAM is particularly significant due to its high speed, low power consumption, and simple operation. In addition, unlike the DRAM, the SRAM has advantages of an easy design as well as not having to regularly refresh stored data.
The SRAM cell generally includes: two drive transistors which are pull-down devices; two access devices; and two pull-up devices. The SRAM is further categorized into three structures: a full CMOS cell; an High Road Resistor (HRL) cell; and a Thin Film Transistor (TFT) cell, according to the type of a pull-up devices used.
The full CMOS cell utilizes a P-channel bulk MOSFET as the pull-up device. The HRL cell utilizes a polysilicon having a high resistance value as the pull-up device, and the TFT cell utilizes a P-channel polysilicon TFT as the pull-up device. Of the above mentioned structures, the SRAM cell with the full CMOS cell structure has a optimal operational device properties and can be fabricated with a relatively simple process. It, however, includes a NMOS and PMOS transistor, resulting in a large cell size. Therefore, it is usually applied to the memory device having a small capacitance, such semiconductor logic devices. On the other hand, the SRAM cell with the HRL cell and the TFT cell structure have relatively poor performance and is complicated in their fabrication. An SRAM cell, however, using the above structures, has the advantage of small cell size and is therefore generally applied to a semiconductor memory devices with larger capacitance.
FIG. 1 is a conventional circuit diagram of an SRAM cell with full CMOS cell structure.
As shown in this diagram, sources S1 and S2 of PMOS transistors Q1 and Q2 for use in pull-up devices are connected to VDD. Drains D1 and D2 of the PMOS transistors Q1 and Q2 are respectively connected in series to each drains D3 and D4 of NMOS transistors Q3 and Q4 for use in pull-down devices at nodes N1 and N2. Sources S1 and S1 of the NMOS transistors Q3 and Q4 are connected to VSS. Gates G1 and G2 of the PMOS transistors Q1 and Q2 are respectively connected to gates G3 and G4 of the NMOS transistors Q3 and Q4, and these connection points thereof are respectively cross-coupled with the nodes N1, N2. In NMOS transistors Q5 and Q6 for use in access devices, Gates G5 and G6 are connected to a word line W/L, sources S5 and S6 are respectively connected to bit lines B/L1 and B/L2. Drains D5 and D6 of NMOS transistors Q5 and Q6 are respectively connected to the drains D3 and D4 of the NMOS transistors Q3 and Q4 at the nodes N1, N2.
In the above described SRAM cell, the NMOS transistors Q5 and Q6 are turned on by turning on the word line W/L, to store data in a HIGH state in the node N1 and data in a LOW state in the node N2. Data in a HIGH state is inputted to the bit line B/L1 and data in a LOW state is inputted to the bit line B/L2, so that the PMOS transistor Q1 and NMOS transistor Q4 are turned on, and PMOS transistor Q2 and NMOS transistor Q3 are turned off. Therefore, the node N1 becomes a HIGH state and the node N2 becomes a LOW state. Furthermore, although the word line W/L is turned off, the node N2 is latched to maintain a LOW state and the node N1 is maintained at a HIGH state. Accordingly, data is stored in the nodes N1 and N2 respectively.
One of the most important factors affecting the performance of the SRAM is an immunity to soft errors. The immunity to the soft errors is determined by a current (I.sub.ON) of the pull-up devices in an on state and cell node capacitance. In case a voltage in a high state VDD of the node N1 is Vh, the current (I.sub.ON) of the pull-up devices and the cell node capacitance influence the an immunity to soft errors as follows.
If the bit line B/L1 is VDD, the NMOS transistor Q5 is turned on. Therefore the Vh is reduced by a threshold voltage (Vt) of the NMOS transistor Q5 thereby decreasing to VDD-Vt. At this time, if amount of current is provided from power supply of the VDD is sufficient, the Vh is increased back to the VDD. Thus, when the Vh is decreased from VDD to VDD-Vt by the turning on of the NMOS transistor Q5, in case of a large cell node capacitance, a rate of decrease from Vh to the VDD-Vt is low. In case of a high I.sub.ON and a large cell node capacitance, a time of the increase back to the VDD is fast.
Conventionally, to prevent hot carrier effect, a source/drain junction region is formed as an LDD structure having a N.sup.- source/drain junction region and a N.sup.+ source/drain junction region to thereby form a grade junction under a gate. In this case, the N.sup.- source/drain region is formed by P ions and the N.sup.+ source/drain junction region is formed by As ions. A concentration profile of P ions is a moderate in nature, so that the junction capacitance is small, and a concentration profile of As ions is very abrupt in nature, so that the junction capacitance is large. Moreover, impurity concentration of the N.sup.+ junction region is 10 to 10.sup.2 times high than that of the N.sup.- junction region, so that the junction capacitance of the former is .sqroot.10 to .sqroot.100 times larger than that of the latter. Because the junction capacitance is proportional to root multiple of a impurity concentration. However, the N.sup.- regions of the source/drain junction regions formed as the grade junction decrease a cell node capacitance in SRAM. Therefore the immunity against soft errors of SRAM decrease.